1. Technical Field
The present invention relates to data communications. More particularly, this invention relates to adaptive control of a PLL loop bandwidth to reduce jitter in high-speed digital data transmission.
2. Description of the Related Art
High-speed digital connections are increasingly used to enable communications between various devices, such as a host and a display. For example, the Digital Visual Interface (DVI), one of the industry standards for video transmission, aims to provide a robust digital link using Transition-Minimized Differential Signaling (TMDS) in an environment where severe jitter is present between a transmitter and a receiver. The transmitter typically uses a phase-locked loop (PLL) to extract data in a bit stream, while the receiver uses a PLL to receive data from the received bit stream. For more details on TMDS, refer to DVI Specification Revision 1.0, Apr. 2, 1999 from Digital Display Working Group (DDWG).
A PLL consists of a phase detector, a loop filter, and a voltage-controlled oscillator (VCO) connected in a feedback loop. The phase detector compares the phase of the input signal with the output signal from the VCO and adjusts the VCO until the phase difference is very small, at which point the VCO phase is locked to the input phase.
Jitter may be present in the system where PLLs are used in the transmitter and the receiver. In order to reduce jitter in such an environment, it is important to use those PLLs whose parameters are compliant to a given specification. An important parameter is a PLL loop bandwidth, which is the cutoff frequency in the frequency response of a PLL loop operation, indicating how fast the PLL loop response is. The transmitter PLL loop bandwidth and the receiver PLL loop bandwidth affect the relative jitter between the transmitter PLL and the receiver PLL.
In a high-speed digital transmission system such as a TMDS system, the transmitter and the receiver share the same clock. However, the instantaneous clock phases at the transmitter and at the receiver may be different. The difference is termed relative jitter, which may cause a bit error if excessive. In general, if the transient response of the transmitter PLL and that of the receiver PLL with respect to the incoming jitter is similar, the relative jitter between the transmitter PLL and the receiver PLL is minimized.
Unfortunately, not every PLL used in such an environment is compliant to specification, resulting in a problematic system solution. For example, although many current product transmitter PLLs are claimed to be DVI/TMDS compliant, some of them are not fully compliant to that specification. To make a PLL whose loop bandwidth complies with a particular specification is not an easy task because it involves not only robust circuit design but also tight control over fabrication process parameters. As a result, there are many cases where the loop bandwidth of the transmitter PLL and that of the receiver PLL do not match, which increases the jitter in the system.
The problem is further compounded by the use of different transmitter architectures. For example, there are two principal schemes for generating a clock sent from the transmitter to the receiver in a digital link using TMDS or the like. One is a coherent clocking scheme where both the clock and the data are generated through a PLL. The other is an incoherent clocking scheme where the data is generated through a PLL but the clock is not. Although the incoherent transmitter architecture may be favored in the DVI specification, coherent transmitter architectures are still available in the market and a novel coherent architecture may emerge. Since the DVI specification is not specific about the coherency, it is important to design a receiver that can support both schemes. Also, it is important for such a feature to support other standards.
For the coherent clocking scheme, the clock recovery circuit in the receiver is required to have as fast a response as possible, such as that provided by a delay locked loop (DLL). If a PLL is used, the loop bandwidth of the PLL should be maximized to make the response as fast as possible. Although reducing absolute jitter may lead to reducing relative jitter, it is not always easy nor guaranteed. Therefore, reducing the relative jitter with a somewhat large absolute jitter level becomes important. Conventional communication schemes are geared for reducing the absolute jitter, the coherent scheme being an example.
A transmitter using the coherent clocking scheme often uses a narrow bandwidth PLL as a clock generator to generate an output clock. The narrow bandwidth PLL usually filters out the jitter in the input clock at the transmitter. As the data rate increases, however, the channel gets more susceptible to high frequency noise sources such as capacitive/inductive coupling, inter-symbol interference, and reflection. Since these interferences are not under the control of the transmitter PLL and are of a wide band nature, the coherent clocking scheme becomes more susceptible to these interferences.
With the incoherent clocking scheme, the clock recovery circuit in the receiver is required to have similar loop characteristics to the PLL in the transmitter. A DLL cannot be used for the clock generating circuitry in the receiver. Instead, either a configurable PLL or DLL/PLL composite architecture preferred. A loop bandwidth mismatch results from unreliable circuit construction or process/temperature/supply voltage variations. Hence, it is desirable that the receiver can adapt to the variation of the transmitter PLL characteristics.
Therefore, there is a need for a scheme that can reduce jitter in a high-speed digital transmission system by adapting the receiver characteristics to the transmitter characteristics, such as the variation in the transmitter PLL and the transmitter clock generation method.